The present invention relates generally to phase or state changeable memory devices and, more particularly, to chalcogenide memory cells.
The use of electrically writable and erasable phase change materials (i.e., materials which can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form) for electronic memory applications is well known in the art and is disclosed, for example, in U.S. Pat. No. 5,296,716 to Ovshinsky et al., the disclosure of which is incorporated herein by reference. U.S. Pat. No. 5,296,716 is believed to generally indicate the state of the art, and to contain a discussion of the current theory of operation of chalcogenide materials.
Generally, as disclosed in the aforementioned Ovshinsky patent, such phase change materials can be electrically switched between a first structural state where the material is generally amorphous and a second structural state where the material has a generally crystalline local order. The material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. That is, the switching of such materials is not required to take place between completely amorphous and completely crystalline states but rather the material can be switched in incremental steps reflecting changes of local order to provide a "gray scale" represented by a multiplicity of conditions of local order spanning the spectrum from the completely amorphous state to the completely crystalline state.
The material exhibits different electrical characteristics depending upon its state. For instance, in its amorphous state the material exhibits a lower electrical conductivity than it does in its crystalline state.
These memory cells are monolithic, homogeneous, and formed of chalcogenide material selected from the group of Te, Se, Sb, and Ge. Such chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods with the input of picojoules of energy. The resulting memory material is truly non-volatile and will maintain the integrity of the information stored by the memory cell without the need for periodic refresh signals. The subject memory material is directly overwritable so that the memory cells need not be erased (set to a specified starting point) in order to change information stored within the memory cells. Finally, the large dynamic range offered by the memory material provides for the gray scale storage of multiple bits of binary information in a single cell by mimicking the binary encoded information in analog form and thereby storing multiple bits of binary encoded information as a single resistance value in a single cell.
The operation of chalcogenide memory cells requires that a region of the chalcogenide memory material, called the chalcogenide active region, be subjected to a current pulse typically with a current density between about 10.sup.5 and 10.sup.6 amperes/cm.sup.2. This current density may be accomplished by creating a small opening 1, referred to as a pore, in a dielectric material 2 which is itself deposited onto a lower electrode material 3 as illustrated in FIG. 1. The chalcogenide material 4 is then deposited over the dielectric material 2 and into the pore 1 into contact with the lower electrode material 3. A top electrode material 5 is then deposited over the chalcogenide material 4. Carbon is a commonly used electrode material although other materials have also been used, for example, molybdenum and titanium nitride. The chalcogenide active region 6 is primarily defined by the volume of chalcogenide material 4 that is contained within the pore 1 defined by the opening in the dielectric material 2. The upper portion 7 of the chalcogenide material 4 not contained within the pore 1 acts as an electrode that in turn contacts with the upper electrode material 5. The chalcogenide active region 6 makes contact with the lower electrode 3 at an interface area 8 that is substantially equal to the cross sectional area of the pore 1.
As a consequence of this configuration, the interface area of the chalcogenide material within the chalcogenide active region is subjected to the high current density required for operation of the chalcogenide memory cell. This is an undesirable situation as the high current density at the interface area of the chalcogenide active region with the lower electrode causes mixing of the lower electrode material with the chalcogenide material of the chalcogenide active region due to heating and electrophoretic effects. The mixing of the electrode material with the chalcogenide material of the chalcogenide active region results in instability of the chalcogenide memory cell in operation.
The present invention is directed to overcoming, or at least reducing the affects of, one or more of the problems set forth above. In particular, the present invention provides a multilevel chalcogenide memory cell with relatively large area chalcogenide electrodes on both sides of the active region of the chalcogenide memory cell thereby reducing the current density at the interface area between the top and bottom electrodes and the chalcogenide material. As a result, the current density and associated heating and electrophoretic effects are minimized.